1. Field of the Invention
The present invention relates to a constant current/constant voltage generation circuit provided in a semiconductor integrated circuit device, and more particularly, to the structure of a circuit generating a bias current for generating a constant voltage.
2. Description of the Background Art
A semiconductor integrated circuit device includes an internal voltage generation circuit for internally generating a reference voltage of a prescribed level. The internal voltage generation circuit internally generates the reference voltage, thereby enabling reduction of a pin count and generation of a reference voltage of the optimum level depending on the operating characteristics of an internal circuit.
FIG. 1 illustrates the structure of a conventional reference voltage generation circuit. Referring to FIG. 1, the conventional reference voltage generation circuit includes a constant voltage generation circuit 1 generating a constant voltage V1 not dependent on a power supply voltage Vcc, and a reference voltage production circuit 2 producing an output voltage Vout when activated in accordance with the constant voltage V1 from constant voltage generation circuit 1.
Constant voltage generation circuit 1 includes a constant current source 1a connected between a power supply node and a node N1 for supplying a constant current, and an N-channel MOS transistor 1b converting the constant current from constant current source 1a to the voltage V1. MOS transistor 1b has a gate and a drain connected to node N1 and operates in a saturation region to set the gate and drain voltages so as to receive and discharge the constant current supplied from constant current source 1a as a drain current. Therefore, the voltage V1 outputted to node N1 reaches a constant level not dependent on power supply voltage Vcc.
Reference voltage production circuit 2 includes an N-channel MOS transistor 2a connected between a node N2 and a ground node with a gate thereof connected to node N1, a P-channel MOS transistor 2b connected between a power supply node and a node N4 and receiving a mode switching signal .phi.A at a gate thereof, a P-channel MOS transistor 2c connected between node N4 and node N2 with a gate thereof connected to node N2, a p-channel MOS transistor 2d connected between node N4 and a node N3 with a gate thereof connected to node N2 and an N-channel MOS transistor 2e connected between node N3 and a ground node with a gate thereof connected to node N3.
MOS transistor 2a forms a current mirror circuit with MOS transistor 1b of constant voltage generation circuit 1, while MOS transistors 2c and 2d form another current mirror circuit. MOS transistor 2e converts a current supplied from MOS transistor 2d to a voltage and produces the output voltage Vout.
Mode switching signal .phi.A is a control signal for activating/inactivating the operation of the reference voltage generation circuit generating the output voltage Vout. Mode switching signal .phi.A is driven to an active low level when activating the operation of generating the reference voltage Vout, and the output voltage Vout is produced in accordance with the voltage V1 on node N1. In an inactive state, mode switching signal .phi.A is set high at the level of power supply voltage Vcc, MOS transistor 2b is turned off and current supply to MOS transistors 2c and 2d is stopped. In this state, node N2 is discharged to a ground voltage level through MOS transistor 2a, while node N3 is also discharged to the ground voltage level through MOS transistor 2e.
The constant voltage generation circuit 1 is simply required to supply the constant voltage V1 to the gate of MOS transistor 2a, and consumes an extremely small current. On the other hand, reference voltage production circuit 2 supplies the reference voltage Vout to a circuit such as a compare circuit or a constant current source. Therefore, the reference voltage production circuit 2 has relatively large current driving capability so as to stably drive a relatively large output load. When MOS transistors 1b and 2a are identical in size to each other, the drain voltage of MOS transistor 2a (i.e., the voltage of node N2) is also equal to the voltage V1. When MOS transistors 2c and 2d are equal in size to each other, the currents of nodes N2 and N3 are equal in magnitude to each other through operation of the current mirror circuit formed by MOS transistors 2c and 2d. Therefore, the level of the output voltage Vout is equal to that of voltage V1 (when MOS transistors 2a and 2e are equal in size to each other). The term "size" indicates the ratio W/L of a gate width W to a gate length L of the MOS transistors.
The reference voltage Vout can be produced in response to the operation of the circuit using the output voltage Vout by selectively activating/inactivating the reference voltage production circuit 2 through mode switching signal .phi.A, thereby reducing current consumption.
FIG. 2 illustrates voltage waveforms in mode switching on respective nodes of the reference voltage generation circuit shown in FIG. 1. In a standby state, mode switching signal .phi.A is set high, MOS transistor 2b is turned off, and the voltage on node N2 and the output voltage Vout go down to the ground voltage. Constant voltage generation circuit 1 regularly operates, and node N1 is set to voltage V1 responsive to the constant current from constant current source 1a.
At a time ta, mode switching signal .phi.A is set to an active low level and MOS transistor 2b is turned on. Thus, a current is supplied to node N2 through MOS transistor 2c, to raise the voltage level of node N2. MOS transistor 2a has a parasitic capacitance Cpr provided by a parallel body of a gate capacitance formed by a gate insulative film and a fringe capacitance formed between a peripheral portion of a source/drain region thereof and a gate electrode thereof. This parasitic capacitance Cpr is connected between node N2 and node N1. When the voltage level of node N2 is raised, therefore, this voltage rise is transmitted to node N1 due to a coupling effect of parasitic capacitance Cpr, to raise the level of the constant voltage V1 on node N1. When the level of the voltage V1 on node N1 is raised, the amount of current flowing through MOS transistors 2c and 2a is increased to increase the amount of current flowing through MOS transistors 2d and 2e, thereby raising the level of the reference voltage Vout outputted from node N3. The voltage of node N2 is raised toward a prescribed level in response to the current supplied through MOS transistors 2c and 2a. Even if the voltage level of node N2 is stabilized, the voltage V1 of node N1 is at a raised level due to the coupling effect of parasitic capacitance Cpr and a relatively long time is required until MOS transistor 1b discharges the voltage of node N1. In a period T when the voltage level of node N1 is higher than a predetermined level, therefore, the level of the reference voltage Vout is also high and a circuit receiving the reference voltage Vout cannot stably operate during this period T. Therefore, when the mode switching signal .phi.A is used for switching the standby state and an active state, for example, an activated internal circuit operates after a lapse of the time T from the time ta in a practical use. Thus, the timing for starting the operation of the internal circuit is disadvantageously delayed.
Such instability of the reference voltage in mode switching in the reference voltage generation circuit having the aforementioned mode switching function also takes place in a structure other than the current mirror type reference voltage generation circuit in general.